1. Field of the Invention
The present invention relates to the forming of RAMs in integrated form. More specifically, the present invention relates to the forming of dynamic random access memories (DRAMs).
2. Discussion of the Related Art
Generally, a DRAM is formed of an array of elementary memory cells located at the intersection of rows (word lines) and columns (bit lines). Each elementary cell is formed of a capacitive memory point (capacitor) and of an element for controlling this memory point, generally, a MOS transistor. The gate of the MOS transistor forms the word line of the cell. The source or drain region of the control transistor is in contact with a first electrode of the capacitor, the other electrode or plate of which is common to all cells in at least one column. The drain or source region of the control transistor is integral with a bit line common to all cells in a column.
Constantly, the amount of elementary cells integrated on a given silicon surface area is desired to be increased as much as possible. For this purpose, it is desired to reduce to the smallest possible the dimensions of an elementary cell. The smallest possible dimension for a conductive line is designated with reference F. This minimum dimension is also called the minimum rule, since it corresponds to a drawing rule imposed to the designer by a used manufacturing technology. Square F2 of minimum rule F thus is the minimum surface area or unity surface area of a pattern. Elementary cells having a surface area which is four times the unity surface area could theoretically be formed. However, in practice, the cells have a much larger size.
A DRAM cell having an integration surface area which is only six times the unity surface area (6 F2) has been proposed in review 2000 IEEE, IEDM, pp. 349 to 352, published on Dec. 10, 2000, in article “An orthogonal 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM” by C. J. Radens et al.
FIG. 1 illustrates, in a partial simplified top view, a memory including such 6F2 cells. More specifically, FIG. 1 illustrates two parallel bit lines BL1, BL2. Each bit line BL1, BL2 has the width of minimum rule F, and is separated from a next bit line BL2, BL1, by twice 2F the minimum rule. Two parallel word lines WL1 and WL2 are separated by this same minimum rule F. Memory points C11, C12, C21, and C22 are formed, as described hereafter in relation with FIGS. 2A to 2E and 3, under the intersections of bit lines BL1, BL2 and word lines WL1, WL2. The 6F2 cell finally includes between every two word lines WL1, WL2 between two memory points C11 and C21, C12 and C22, a bit line contact BLC1, BLC2.
FIGS. 2A to 2E illustrate, in a partial simplified cross-section view along axis A—A of FIG. 1, that is, an axis running in bit line BL2, successive steps of a method for forming such a 6F2 cell. FIG. 3 is a cross-section view along axis B—B of FIG. 1, parallel to axis A—A, above memory points C12 and C22 sharing the same bit line BL2, but outside of this bit line. FIG. 3 corresponds to an intermediary step between those illustrated in FIGS. 2C and 2D.
As illustrated in FIG. 2A, an N-type doped region 2 is first formed, generally by epitaxy, on a semiconductor substrate 1, typically made of silicon, of a first conductivity type, conventionally type P. Region 2 is buried under a P-type surface region or well 3. Buried region 2 is intended to be used as a plate electrode of the memory point. Then, a trench 4 is dug into well 3, region 2, and substrate 1. The definition of the location and of the dimensions of trench 4 is performed by means of the first mask.
A silicon oxide insulating ring 5 is then formed on a high portion of the walls of trench 4. An insulator 6 with a high electric permittivity is then deposited on the bottom and walls of trench 4. A heavily-doped N-type peripheral region 7 is formed in substrate 1 and region 2, around the low portion of trench 4. Then, a conductive material 8, generally polysilicon, is deposited at the bottom of trench 4. An elementary memory point having an electrode 7 connected by region 2 to the similar electrodes of several cells and separated by a dielectric 6 from a second electrode 8 specific to each memory point is thus formed.
At the next steps, illustrated in FIG. 2B, insulator 5 is removed from a high portion of one of the walls of trench 4, for example, the left-hand wall. A conductive material 9, identical to material 8, generally polysilicon, is deposited and etched. Material 9 is in contact by its low portion with electrode 8. This low portion is insulated from the peripheral silicon (well 3, region 2) by ring 5. Material 9 is in contact in its high portion with well 3 along the wall from which insulator 5 has been removed. A heavily-doped N-type region 10 is formed in well 3 by diffusion from material 9.
Then, a thick insulator is formed on material 9. Insulator 11 aims at insulating material 9 from any parasitic coupling with conductive structures formed at the next steps in the upper portion of trench 4. Region 10, which is diffused from material 9, extends to the top of the structure (surface of well 3) beyond thick insulator 11.
At the newt steps, illustrated in FIG. 2C, a thin insulator 12 is formed on the exposed wall of trench 4 and on the planar horizontal surface of well 3. A heavily-doped N-type region 13 is then implanted at the surface of well 3. Then, a conductive material 14, generally polysilicon, is deposited. Material 14 is intended to be used as the control transistor gate, insulator 12 being the gate insulator between gate 14 and vertical well 3.
The result of next steps is illustrated in FIG. 3, which is a cross-section view along line B—B of FIG. 1. Well 3 has been dug into, as well as a portion of the multiple-layer formed in trench 4, to open a shallow insulating trench 15 (STI) filled with an insulator. Insulating trench 15 is formed to extend in depth beyond contact level 9 and to reach insulating ring 5. The second mask used to dig into insulating trench 15 must thus be precisely aligned with respect to the first mask used (FIG. 2A) to dig into trench 4. The forming of insulating trenches 15 enables individualizing neighboring elementary cells.
As illustrated in FIG. 2D, gate 14 is then completed, for example, by forming a tungsten silicide layer 16 and an insulating layer 171. Then, by means of a third mask which must be precisely aligned with respect to the first and second masks, the multiple layer formed of layers 14-16-171 is etched to define (individualize) the word lines of each of the elementary cells. Gate 14-16-171 is then provided on its vertical walls with an insulating structure 172, generally of same nature as insulating layer 171. A thick interlevel insulating or dielectric layer 18 is then deposited so that its surface is substantially planar. Interlevel dielectric 18 is of different nature than the insulator forming layer 171 and vertical insulating structure 172, to be selectively etchable with respect thereto.
At the next steps, illustrated in FIG. 2E, the method carries on with the opening of interlevel dielectric 18 by means of a fourth mask, to partially expose surface regions 13. The fourth mask must again be precisely aligned with respect to the three preceding masks. A conductive material 19 is deposited on dielectric 18 to at least fill the openings. Finally, material 19 is etched by means of a fifth mask to define above dielectric 18 bit line contacts with source or drain regions 13. The central contact illustrated in FIG. 2E is contact BLC2 of FIG. 1. The alignment of the fifth mask must also be precisely performed with respect to the preceding masks.
A memory point having, as a control element, a MOS transistor with a substantially vertical channel has thus been formed, as illustrated in FIG. 2E. Heavily-doped surface region 13 forms a source region of the transistor. The drain region of the transistor is formed by region 10. This transistor includes a control gate 14 insulated from the channel region by a thin insulator 12. This control transistor enables possibly putting in contact a bit line 19 with first electrode 9-8 of a memory point having its second electrode or plate corresponding to regions 7 and 2.
Such a formation method is relatively complex due to the five masks successively used, which must be precisely aligned with respect to one another.
The use of such masks further results in the forming of elementary cells having six times the unity surface area, instead of four times as would theoretically be possible.